1. Field
Exemplary embodiments of the present invention relate to a base chip and a semiconductor package including the same.
2. Description of the Related Art
A memory cell of a semiconductor memory device includes a transistor serving as a switch and a capacitor for storing an electric charge representing data. More specifically, according to whether or not an electric charge is stored in the capacitor of the memory cell or whether the terminal voltage of the capacitor is high or low, the data is determined to be high (logic 1) or low (logic 0).
In principle, since data is stored as an accumulated electric charge, no power is consumed for maintaining the stored data. However, in practice, an initial charge stored in the capacitor may degrade due to a leakage current caused by the PN junction of a metal oxide semiconductor (MOS) transistor. As a result the data may be lost. In order to prevent such a data loss, the stored data in the memory cell must be read, and the memory cell must be recharged according to the read information, before the data is lost. Such an operation must be periodically repeated to retain the data. The process of recharging the memory cell is commonly known as a refresh operation.
In general, a semiconductor memory device performs a refresh operation by periodically activating a word line, in order to retain data stored in memory cells coupled to the word line. A semiconductor memory device includes a plurality of memory banks each having a plurality of word lines. When all memory banks of the semiconductor memory device simultaneously activate word lines in order to perform a refresh operation, the peak current used in the semiconductor memory device may significantly rise.
FIG. 1 is a diagram illustrating a plurality of memory banks BK0 to BK15 included in a semiconductor memory device. FIGS. 2A to 2C are diagrams for illustrating a piled refresh operation.
Referring to FIG. 1, the memory banks BK0 to BK15 may perform a refresh operation when corresponding refresh signals among a plurality of refresh signals REF0 to REF15 are activated.
Referring to FIG. 2A, the refresh operations of the memory banks BK0 to BK15 included in the semiconductor memory device are performed at the same time. Thus, the peak current used in the semiconductor memory device is very high.
Referring to FIG. 28, the plurality of memory banks BK0 to BK15 included in the semiconductor memory device is divided into four groups, and refresh operations of the four groups are sequentially performed. Thus, the peak current used in the semiconductor memory device is lowered compared to the case of FIG. 2A.
Referring to FIG. 2C, the plurality of memory banks BK0 to BK15 included in the semiconductor memory device is divided into 16 groups, and refresh operations of the 16 groups are sequentially performed. Thus, the peak current used in the semiconductor memory device is lowered even more compared to the cases of FIGS. 2A and 28.
FIG. 3 is a diagram illustrating a semiconductor package including a plurality of chips, a base chip BASE and a plurality of core chips CORE0 to CORE3.
Referring to FIG. 3, the plurality of core chips CORE0 to CORE3 each core chip including a plurality of memory banks (not shown) are sequentially stacked over the base chip BASE. The base chip BASE performs communication between the semiconductor package and an external device. The base chip BASE may generate signals for controlling the plurality of core chips CORE0 to CORE3 in response to a command received from the external device, and transmit the generated signals to the respective core chips through a plurality of Through Silicon Vias (TSVs). In this example, the signals for controlling the plurality of core chips CORE0 to CORE3 may include a signal for controlling the above-described refresh operation.
In the semiconductor package, the number of memory banks which must be controlled by the base chip BASE may differ according to the number of stacked core chips. Furthermore, when the number of TSVs is increased to control the memory banks, the area of the chip may be significantly increased.